High-Level Synthesis from the Synchronous Language Esterel

Producing efficient circuits from high-level language descriptions remains a problem. This paper proposes three techniques for improving the quality of circuits generated from high-level Esterel specifications, a synchronous, concurrent language designed to specify control-dominated systems. Together, the three techniques aim to improve the quality of the input to logic synthesis to produce better results. The first uses control dependence information to synthesize small, fast circuits from control-flow graphs. The second involves solving the state assignment problem for Esterel-derived circuits at a much higher level than has previously been proposed, allowing many more optimization opportunities. The third technique extracts don’t-care information from high-level representations to improve the quality of logic synthesis. I believe these techniques will make Esterel a compelling alternative to existing RTL synthesis languages.